Advances in semiconductor processing have demanded ever-increasing high functional density with continuous size scaling. This scaling process has led to the adoption of high-k gate dielectrics and metal gate electrodes in metal gate stacks in semiconductor devices.
High-k gate dielectrics can offer a way to scale down the thickness of the gate dielectric with acceptable gate leakage current. The use of high-k gate dielectrics is often accompanied by a metal gate electrode, since thin gate dielectric layers may cause poly depletion, affecting the device operation and performance.
The introduction of metal elements to the device, e.g., in the formation of the metal gate electrode, can impose significant changes to the device fabrication process, including device structure designs to reduce leakage, process chemistry to pattern metallic structures and avoid metal corrosion, and cleaning chemistry to remove metallic-containing residues.
Further, advanced semiconductor devices also use advanced gate dielectric in addition to the metal gate electrode. The advanced gate dielectric can comprise ultra-thin silicon dioxide, for example, less than 5 nm thick, which poses tunneling problems. The advanced gate dielectric can comprise a high-k material, which imposes additional challenges to the device fabrication process. For example, in some portions of the fabrication, etch processes with very high selectivity chemistries and conditions are needed, for example, to avoid gate dielectric punch through or to avoid damage to the device, such as corner damage to the metal gate structure.
The manufacture of high-k dielectric and metal gate devices entails the integration and sequencing of many unit processing steps, with potential new process developments, since in general, high-k gate dielectrics are much more sensitive to process conditions than silicon dioxide. For example, the precise sequencing and integration of the unit processing steps can enable the formation of functional devices meeting desired performance metrics such as power efficiency, signal propagation, and reliability.
As part of the discovery, optimization and qualification of each unit process, it is desirable to be able to i) test different materials, ii) test different processing conditions within each unit process module, iii) test different sequencing and integration of processing modules within an integrated processing tool, iv) test different sequencing of processing tools in executing different process sequence integration flows, and combinations thereof in the manufacture of devices such as integrated circuits. In particular, there is a need to be able to test i) more than one material, ii) more than one processing condition, iii) more than one sequence of processing conditions, iv) more than one process sequence integration flow, and combinations thereof, collectively known as “combinatorial process sequence integration”, on a single monolithic substrate without the need of consuming the equivalent number of monolithic substrates per material(s), processing condition(s), sequence(s) of processing conditions, sequence(s) of processes, and combinations thereof. This can greatly improve both the speed and reduce the costs associated with the discovery, implementation, optimization, and qualification of material(s), process(es), and process integration sequence(s) required for manufacturing.
HPC processing techniques have been successfully adapted to wet chemical processing such as etching and cleaning. HPC processing techniques have also been successfully adapted to deposition processes such as physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD). However, HPC processing techniques have not been successfully adapted to the development of wet chemicals to post metal gate etch clean development.
Therefore, there is a need to apply high productivity combinatorial techniques to the development and investigation of liquid materials and wet processes for the manufacture of high-k and metal gate devices.